Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to a capacitor structure for power delivery applications.
Background
The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processes. The front-end-of-line process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The middle-of-line process may include gate contact formation. Middle-of-line layers may include, but are not limited to, middle-of-line contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The back-end-of-line process may include a series of wafer processing steps for interconnecting the semiconductor devices created during the front-end-of-line and middle-of-line processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.
For integrated circuits in wireless communications devices or other high-speed digital electronics, a power delivery network supplies power to the various components of the overall system. A power delivery network may include a voltage regulator module that regulates voltage for a component. Resonance in a power delivery network is undesirable. Suppressing resonance in a power delivery network may be performed using a capacitor. Surface mount technology (SMT) capacitors may reduce power delivery network resonance/noise in high power, system on chip devices, such as application processors and graphics processors.